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open-scope-samplescaling.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 00:33:04 November 02, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# open-scope-samplescaling_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C5E144C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:02:10 NOVEMBER 02, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name SDC_FILE SDC1.sdc
set_global_assignment -name VHDL_FILE i2c_Master.vhd
set_global_assignment -name VHDL_FILE edgedetect.vhd
set_global_assignment -name VHDL_FILE common.vhd
set_global_assignment -name VHDL_FILE vga_640x480.vhd
set_global_assignment -name VHDL_FILE trigger_system2.vhd
set_global_assignment -name VHDL_FILE sample_RAM.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_69 -to RAM_A[10]
set_location_assignment PIN_50 -to RAM_A[11]
set_location_assignment PIN_59 -to RAM_nWE
set_location_assignment PIN_51 -to RAM_A[9]
set_location_assignment PIN_52 -to RAM_A[8]
set_location_assignment PIN_53 -to RAM_A[7]
set_location_assignment PIN_58 -to RAM_A[6]
set_location_assignment PIN_55 -to RAM_A[5]
set_location_assignment PIN_54 -to RAM_A[4]
set_location_assignment PIN_71 -to RAM_A[3]
set_location_assignment PIN_72 -to RAM_A[2]
set_location_assignment PIN_73 -to RAM_A[1]
set_location_assignment PIN_70 -to RAM_A[0]
set_location_assignment PIN_67 -to RAM_BA0
set_location_assignment PIN_68 -to RAM_BA1
set_location_assignment PIN_44 -to RAM_CKE
set_location_assignment PIN_43 -to RAM_CLK
set_location_assignment PIN_33 -to RAM_DQ[7]
set_location_assignment PIN_34 -to RAM_DQ[6]
set_location_assignment PIN_38 -to RAM_DQ[5]
set_location_assignment PIN_39 -to RAM_DQ[4]
set_location_assignment PIN_74 -to RAM_DQ[3]
set_location_assignment PIN_75 -to RAM_DQ[2]
set_location_assignment PIN_76 -to RAM_DQ[1]
set_location_assignment PIN_77 -to RAM_DQ[0]
set_location_assignment PIN_42 -to RAM_DQM
set_location_assignment PIN_60 -to RAM_nCAS
set_location_assignment PIN_66 -to RAM_nCS
set_location_assignment PIN_64 -to RAM_nRAS
set_location_assignment PIN_91 -to CLK_25
set_location_assignment PIN_11 -to AD_CLK
set_location_assignment PIN_1 -to AD_data[8]
set_location_assignment PIN_2 -to AD_data[6]
set_location_assignment PIN_3 -to AD_data[4]
set_location_assignment PIN_4 -to AD_data[2]
set_location_assignment PIN_7 -to LED[3]
set_location_assignment PIN_10 -to AD_data[0]
set_location_assignment PIN_24 -to CLK_32
set_location_assignment PIN_28 -to AD_data[10]
set_location_assignment PIN_30 -to AD_data[9]
set_location_assignment PIN_31 -to LED[2]
set_location_assignment PIN_32 -to AD_data[11]
set_location_assignment PIN_46 -to LED[0]
set_location_assignment PIN_49 -to RAM_A[12]
set_location_assignment PIN_80 -to KEY[1]
set_location_assignment PIN_65 -to LED[1]
set_location_assignment PIN_79 -to AD_data[7]
set_location_assignment PIN_142 -to AD_data[5]
set_location_assignment PIN_119 -to KEY[0]
set_location_assignment PIN_83 -to ADV_LRCLK
set_location_assignment PIN_84 -to ADV_SCLK
set_location_assignment PIN_86 -to ADV_VSYNC
set_location_assignment PIN_85 -to ADV_I2SD
set_location_assignment PIN_98 -to ADV_DE
set_location_assignment PIN_99 -to ADV_D[0]
set_location_assignment PIN_113 -to ADV_CLK
set_location_assignment PIN_138 -to ADV_D[23]
set_location_assignment PIN_137 -to ADV_D[22]
set_location_assignment PIN_135 -to ADV_D[21]
set_location_assignment PIN_133 -to ADV_D[20]
set_location_assignment PIN_132 -to ADV_D[19]
set_location_assignment PIN_129 -to ADV_D[18]
set_location_assignment PIN_128 -to ADV_D[17]
set_location_assignment PIN_127 -to ADV_D[16]
set_location_assignment PIN_126 -to ADV_D[15]
set_location_assignment PIN_125 -to ADV_D[14]
set_location_assignment PIN_124 -to ADV_D[13]
set_location_assignment PIN_121 -to ADV_D[12]
set_location_assignment PIN_120 -to ADV_D[11]
set_location_assignment PIN_115 -to ADV_D[10]
set_location_assignment PIN_114 -to ADV_D[9]
set_location_assignment PIN_112 -to ADV_D[8]
set_location_assignment PIN_111 -to ADV_D[7]
set_location_assignment PIN_110 -to ADV_D[6]
set_location_assignment PIN_104 -to ADV_D[5]
set_location_assignment PIN_106 -to ADV_D[4]
set_location_assignment PIN_103 -to ADV_D[3]
set_location_assignment PIN_101 -to ADV_D[2]
set_location_assignment PIN_100 -to ADV_D[1]
set_location_assignment PIN_144 -to AD_data[1]
set_location_assignment PIN_143 -to AD_data[3]
set_location_assignment PIN_87 -to ADV_HSYNC
set_location_assignment PIN_136 -to SDA
set_location_assignment PIN_141 -to SCL
set_location_assignment PIN_105 -to SW
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top