iio: adc: ltc2387: Update calculation of duty_offset_ns value #2728
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PR Description
For the situation when the maximum sampling is used, 15MHz.
Before: duty_offset_ns = 70, period_length_ns = 67 (rounded from 66.666)
That caused "ltc2387 setup failed", because the PWM framework has a condition
if wf->duty_offset_ns >= wf->period_length_ns, which is true => fail.
In the case of LTC2387 with max sample rate,
tFIRSTCLK >= 65ns and tCONV = 63ns (data sheet, page 5).
This doesn't go by the PWM framework condition, so the offset needs to be updated, affecting the timing of the cnv and clk_gate signals only at the max sample rate. Just the first time the conversion is affected, being delayed.
Now: duty_offset_ns = 3, period_length_ns = 67.
The first sample is junk anyway.
This doesn't affect the sampling, because it is started by the PWM core before the DMA buffer is enabled.
I tested this on a CN0577/Zed setup and it works (I can provide screenshots if necessary).
PR Type
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